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1 ds04-21309-4e fujitsu semiconductor data sheet assp serial input pll frequency synthesizer mb1511 n description the fujitsu mb1511 is a single chip serial input pll frequency synthesizer designed for vhf tuner and cellular telephone applications. it contains a 1.1 ghz dual modulus prescaler which enables pulse swallow function, and an analog switch to speed up lock up time. it operates supply voltage of 3.0 v typ. and dissipates 7 ma typ. of current realized through the use of fujitsu's unique u-esbic bi-cmos technology. the mb1511 is housed in ssop package, this enables high integration. n features ? low power supply voltage: v cc = 2.7 to 5.5 v ? high operating frequency: f in max = 1.1 ghz (v in min = C10dbm) ? pulse swallow function: 64/65 or 128/129 ? low supply current: i cc = 7 ma typ. serial input 18-bit programmable divider consisting of: binary 7-bit swallow counter: 0 to 127 binary 11-bit programmable counter: 16 to 2047 ? serial input 15-bit programmable reference divider consisting of: binary 14-bit programmable reference counter: 8 to 16383 1-bit switch counter (sw) sets divide ratio of prescaler (continued) n package (fpt-20p-m03) 20 pin, plastic ssop
2 mb1511 (continued) ? on-chip analog switch achieves fast lock up time ? 2 types of phase detector output on-chip charge pump (bipolar type) output for external charge pump ? wide operating temperature: C40c to +85c ? 20-pin plastic shrink small outline package (suffix: Cpfv)
3 mb1511 n pin assignment 1 f r 20 osc in 2 nc 19 nc 3 f p 18 osc out 4 fout 17 v p 5 bisw 16 v cc 6 fc 15 d o 7 le 14 gnd 8 data 13 ld 9 nc 12 nc 10 clock 11 fin (fpt-20p-m03) (top view)
4 mb1511 n pin description pin no. pin name i/o functions 1osc in i oscillator input. oscillator output. a crystal is placed between osc in and osc out . 3osc out o 4v p power supply input for charge pump and analog switch. 5v cc power supply voltage input. 6d o o charge pump output. the characteristics of charge pump is reversed depending upon fc input. 7 gnd ground. 8ldo phase comparator output. normally this pin outputs high level. while the phase difference of fr and fp exists, this pin outputs low level. 10 fin i prescaler input. the connection with an external vco should be ac connection. 11 clock i clock input for 19-bit shift register and 16-bit shift register. on rising edge of the clock shifts one bit of data into the shift registers. 13 data i binary serial data input. the last bit of the data is a control bit which specified destination of shift reg- isters. when this bit is high level and le is high level, the data stored in shift regis- ter is transferred to 15-bit latch. when this bit is low level and le is high level, the data is transferred to 18-bit latch. 14 le i load enable input (with internal pull up resistor). when le is high or open, the data stored in shift register is transferred into latch depending upon the control bit. at the time, internal charge pump out- put is connected to bisw pin because internal analog switch becomes on state. 15 fc i phase select input of phase comparator (with internal pull up resistor). when fc is low level, the characteristics of charge pump, phase comparator is reversed. fc input signal controls fout pin (test pin) output level, fr or fp. 16 bisw o analog switch output. usually bisw pin is set high-impedance state. when internal analog switch is on (le pin is high level), this pin outputs internal charge pump output. 17 fout o minitor pin of phase comparator input. fout pin outputs either programmable reference divider output (fr) or pro- grammable divider output (fp) depending upon fc pin input level. fc = h: it is the same as fr output level. fc = l: it is the same as fp output level. 18 f p o output for external charge pump. the characteristics are reversed according to fc input. f p pin is n-channel open drain output. 20 f ro 2, 9 12, 19 nc no connection.
5 mb1511 n block diagram f r binary 14-bit reference counter programmable reference divider 19 bit shift register 19 bit shift register 7 bit latch 18 bit latch binary 7 bit swallow counter control circuit binary 11 bit programmable counter programmable s w control 1 bit latch data clock prescaler f in osc in osc out le gnd v cc f p v p d o bisw fc ld : data signal : control signal cristal oscillator 11 bit latch charge pump 16 bit shift register 16 bit shift register 15 bit latch 15 bit latch monitor frequency changing circuit analog switch fr fp f out phase comparator 11 13 10 3 1 14 7 5 17 15 8 20 18 16 4 6
6 mb1511 n functional descriptions 1. pulse swallow function the divide ratio is set using the following equation. f vco = [(m n) + a] f osc ? r f vco : output frequency of external voltage controlled oscillator (vco) m : preset modulus of external dual modulus prescaler (64 or 128) n : preset divide ratio of binary 11-bit programmable counter (16 to 2047) a : preset divide ratio of binary 7-bit swallow counter (0 a 127, a < n) f osc : output frequency of the external reference frequency oscillator r : preset divide ratio of binary 14-bit programmable reference counter (8 to 16383) 2. serial data input serial data input is achieved by three inputs, such as data pin, clock pin and le pin. serial data input controls 15- bit programmable reference divider and 18-bit programmable divider, respectively. binary serial data is input to data pin. on rising edge of clock shifts one bit of serial data into the internal shift registers and when load enable pin is high level or open, stored data is transferred into latch depending upon the control bit. control data "h" data is transferred into 15-bit latch. control data "l" data is transferred into 18-bit latch.
7 mb1511 (1) programmable reference divider programmable reference divider consists of 16-bit shift register, 15-bit latch and 14-bit reference counter. serial 16- bit data format is shown below. cs 1 s 2 s 3 s 4 s 5 s 6 s 7 s 8 s 9 s 10 s 11 s 12 s 13 s 14 s w divide ratio of prescaler setting bit msb lsb control bit 00000000001000 00000000001001 11111111111111 8 9 16383 divide ratio less than 8 is prohibited. divide ratio: 8 to 16383 sw: this bit selects divide ratio of prescaler. sw = h: 64/65 sw = l: 128/129 s1 to s14: these bits select divide ratio of programmable reference divider. c: control bit (sets as high level). data is input from msb side. s 14 s 13 s 12 s 11 s 10 s 9 s 8 s 7 s 6 s 5 s 4 s 3 s 2 s 1 divide ratio r divide ratio of programmable reference counter setting bit 14-bit programmable reference counter divide ratio notes: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
8 mb1511 (2) programmable divider programmable divider consists of 19-bit shift register, 18-bit latch, 7-bit swallow counter and 11-bit programmable counter. serial 19-bit data format is shown following page. 3. serial data input timing * : paranthesis data is used for setting divide ratio of programmable reference divider. on rising edge of clock shifts one bit of data in the shift register. cs 1 s 2 s 3 s 4 s 5 s 6 s 7 s 8 s 9 s 10 s 11 s 12 s 13 s 14 msb lsb control bit 00000010001 00000010001 11111111111 16 17 2047 divide ratio less than 16 is prohibited. divide ratio: 16 to 2047 s1 to s7: swallow counter divide ratio setting bit. (0 to 127) s8 to s18: programmable counter divide ratio setting bit. (16 to 2047) c: control bit (sets as low level). data is input from msb side. s 18 s 17 s 16 s 15 s 14 s 13 s 12 s 11 s 10 s 9 s 8 divide ratio n divide ratio of swallow counter setting bit divide ratio of programmable counter setting bit s 15 s 16 s 17 s 18 11-bit programmable counter divide ratio 0000000 0000001 1111111 0 1 127 7-bit swallow counter divide ratio s 7 s 6 s 5 s 4 s 3 s 2 s 1 divide ratio a notes: note: divide ratio: 0 to 127 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? t 2 t 1 t 3 t 4 t 5 data clock le t 1 ~t 5 3 1 m s s18 = msb s17 s10 s9 s1 = lsb c : control bit (c : control bit) (s14) * (sw) (s8) (s7) (s1)
9 mb1511 4. phase characteristics fc pin is provided to change phase characteristics of phase comparator. characteristics of internal charge pump output level (d o ), phase comparator output level ( f r, f p) are reversed depending upon fc pin input level. also, monitor pin (f out ) output level of phase comparator is controlled by fc pin input level. the relation between outputs (d o , f r, f p) and fc input level are shown below. note: z = (high impedance) depending upon vco characteristics, fc pin should be set accordingly: fc : h or open fc : l d o f r f p fout d o f r f pfout fr > fp h l l (fr) l h z (fp) fr = fp z l z (fr) z l z (fp) fr < fp l h z (fr) h l l (fp) vco output frequency vco input voltage (2) (1) ? when vco characteristics are like (1), fc should be set high or open circuit; when vco characteristics are like (2), fc should be set low.
10 mb1511 phase comparator output waveforms are shown below. notes: phase difference detection range: C2 p to +2 p spike appearance depends on charge pump characteristics. also, the spike is output in order to diminish dead band. when fr>fp or fr fp fp ld d o z h l fr = fp fr < fp fr < fp fr < fp charge pump lpf-1 lpf-2 vco analog sw d o bisw (control signal le)
11 mb1511 n absolute maximum ratings (see warning) warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. n recommended operating conditions warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the devices electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. handling precautions ? this device should be transported and stored in anti-static containers. ? this is static-sensitive device; take proper anti-esd precautions. ensure that personnel and equipment are properly grounded. cover workbenches with grounded conductive mats. ? always turn the power supply off before inserting or removing the device from its socket. ? protect leads with a conductive sheet when handing or transporting pc boards with devices. parameter symbol rating unit min. max. power supply voltage v cc C0.5 +7.0 v v p v cc +10.0 v output voltage v out C0.5 v cc +0.5 v open-drain voltage v oop C0.5 +8.0 v output current i out C10 +10 ma storage temperature tstg C55 +125 c parameter symbol value unit min. typ. max. power supply voltage v cc 2.7 3.0 5.5 v v p v cc 8.0 v input voltage v in gnd v cc v operating temperature ta C40 +85 c
12 mb1511 n electrical characterinstics (v cc = 2.7 v to 5.5 v, ta = C40 c to +85 c) *1 : fin =1.1 ghz, osc in =12 mhz, v cc =3v. inputs are grounded and outputs are open. *2 : ac coupling. minimum operating frequency is measured when a capacitor 1000pf. *3 : v cc =4.0 to 5.5v, 50 ( w) *4 : v cc =2.7 to 4.0v, 50 ( w) *5 : v cc =3v *6 : v p =v cc to 8v, v oop =gnd to 8v parameter symbol values unit min. typ. max. power supply current* 1 i cc 7.0ma operating frequency fin* 2 f in 10 1100 mhz osc in f osc 1220mhz input sensitivity fin-1* 3 v fin1 C4 6 dbm fin-2* 4 v fin2 C10 6 dbm osc in v osc 0.5 v p-p high-level input voltage except fin and osc in v ih v cc 0.7 v low-level input voltage v il v cc 0.3 v high-level input current data, clock i ih 1.0 m a low-level input current i il C1.0 m a input current osc in i osc 50 m a le, fc i le C60 m a high-level output voltage except d o and osc out v oh * 5 2.2 v low-level output voltage v ol 0.4v n-channel open drain cutoff current d o , f p* 6 i off 1.1 m a output current except d o and osc out i oh C1.0 ma i ol 1.0 ma analog switch on resistance r on 25 w
13 mb1511 n measurment circuit p ?g 50 w 1000 pf 0.1 m f v cc = 3 v x'tal v p = 6 v oscilloscope 14 13 11 10 7 5 4 3 1 17
14 mb1511 n typical application example v px , v p :8 v max. c 1 , c 2 : depends on crystal oscillator le, fc : with internal pull up resistor f p : open drain output l p f v c o x'tal 20 f r 18 f p 17 fout 16 bisw 15 fc 14 le 13 data 11 clock 1 3 4 5 6 7 8 10 osc in osc out v p v cc d o gnd ld fin mb1511 10 k w 12 k w 12 k w 10 k w output from controller 47 k w 47 k w 1000 pf v cc (3 v) lock detector 0.01 m f 33 k w 100 k w 10 k w 6 v 3 v 0.1 m f c 1 c 2 v px (6v)
15 mb1511 n ordering information part number package remarks mb1511pfv 20-pin plastic ssop (fpt-20p-m03)
16 mb1511 n package dimension 20 pin, plastic ssop (fpt-20p-m03) c 1999 fujitsu limited f20012s-3c-5 6.50?.10(.256?004) * 4.40?.10 6.40?.20 (.252?008) (.173?004) * .049 ?004 +.008 ?.10 +0.20 1.25 (mounting height) 0.10(.004) 0.65(.026) 0.24?.08 (.009?003) 1 10 20 11 "a" 0.10?.10 (stand off) 0.17?.03 (.007?001) m 0.13(.005) (.004?004) details of "a" part 0~8 (.018/.030) 0.45/0.75 (.020?008) 0.50?.20 0.25(.010) lead no. index dimensions in mm (inches). note1) *: this dimension does not include resin protruction. note2) pins width and pins thickness include plating thickness.
mb1511 fujitsu limited all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. the products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). please note that fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan. f 0104 ? fujitsu limited printed in japan

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